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ISL6622A
Data Sheet March 19, 2009 FN6601.2
VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers
The ISL6622A is a high frequency MOSFET driver designed to drive upper and lower power N-Channel MOSFETs in a synchronous rectified buck converter topology. The advanced PWM protocol of ISL6622A is specifically designed to work with Intersil VR11.1 controllers and combined with N-Channel MOSFETs, form a complete core-voltage regulator solution for advanced microprocessors. When ISL6622A detects a PSI protocol sent by an Intersil VR11.1 controller, it activates Diode Emulation (DE) operation; otherwise, it operates in normal Continuous Conduction Mode (CCM) PWM mode. In the 8 Ld SOIC package, the ISL6622A drives the upper gate to 12V while the lower get can be driven from 5V to 12V. The 10 Ld DFN part allows for more flexibility. The upper gate can be driven from 5V to 12V using the UVCC pin and the lower gate can also be driven from 5V to 12V using the LVCC pin. This provides the flexibility necessary to optimize applications involving trade-offs between gate charge and conduction losses. To further enhance light load efficiency, the ISL6622A enables diode emulation operation during PSI mode. This allows Discontinuous Conduction Mode (DCM) by detecting when the inductor current reaches zero and subsequently turning off the low side MOSFET to prevent it from sinking current. An advanced adaptive shoot-through protection is integrated to prevent both the upper and lower MOSFETs from conducting simultaneously and to minimize dead time. The ISL6622A has a 20k integrated high-side gate-to-source resistor to prevent self turn-on due to high input bus dV/dt. This driver adds an overvoltage protection feature operational while VCC is below its POR threshold; the PHASE node is connected to the gate of the low side MOSFET (LGATE) via a 10k resistor limiting the output voltage of the converter close to the gate threshold of the low side MOSFET, dependent on the current being shunted, which provides some protection to the load should the upper MOSFET(s) become shorted.
Features
* Dual MOSFET Drives for Synchronous Rectified Bridge * Advanced Adaptive Zero Shoot-Through Protection * 36V Internal Bootstrap Schottky Diode * Diode Emulation For Enhanced Light Load Efficiency * Bootstrap Capacitor Overcharging Prevention * Supports High Switching Frequency - 3A Sinking Current Capability - Fast Rise/Fall Times and Low Propagation Delays * Advanced PWM Protocol (Patent Pending) to Support PSI Mode, Diode Emulation, Three-State Operation * Pre-POR Overvoltage Protection for Start-up and Shutdown * VCC Undervoltage Protection * Expandable Bottom Copper Pad for Enhanced Heat Sinking * Dual Flat No-Lead (DFN) Package - Near Chip-Scale Package Footprint; Improves PCB Efficiency and Thinner in Profile * Pb-Free (RoHS Compliant)
Applications
* High Light Load Efficiency Voltage Regulators * Core Regulators for Advanced Microprocessors * High Current DC/DC Converters * High Frequency and High Efficiency VRM and VRD
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Technical Brief TB417 "Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators" for Power Train Design, Layout Guidelines, and Feedback Compensation Design
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6622A Ordering Information
PART NUMBER (Note) ISL6622ACBZ* ISL6622ACRZ* ISL6622AIBZ* ISL6622AIRZ* PART MARKING 6622A CBZ 622A 6622A IBZ 22AI TEMP. RANGE (C) 0 to +70 0 to +70 -40 to +85 -40 to +85 8 Ld SOIC 10 Ld 3x3 DFN 8 Ld SOIC 10 Ld 3x3 DFN PACKAGE (Pb-Free) PKG. DWG. # M8.15 L10.3x3 M8.15 L10.3x3
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
ISL6622A (8 LD SOIC) TOP VIEW
UGATE BOOT PWM GND 1 2 3 4 8 7 6 5 PHASE VCC LVCC LGATE UGATE BOOT NC PWM GND 1 2 3 4 5 PAD
ISL6622A (10 LD 3x3 DFN) TOP VIEW
10 PHASE 9 8 7 6 VCC UVCC LVCC LGATE
Block Diagrams
ISL6622A
UVCC
BOOT UGATE 20k
VCC +5V PRE-POR OVP FEATURES 11.2k PWM POR/ CONTROL 9.6k LOGIC SHOOTTHROUGH PROTECTION
PHASE
LVCC LVCC 10k
LGATE
GND
UVCC = VCC FOR SOIC
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FN6601.2 March 19, 2009
ISL6622A Typical Application Circuit
+12V +5V BOOT LVCC VIN
+5V
VCC
UGATE PHASE ISL6622A DRIVER LGATE
FB
COMP VCC
DAC REF
PWM
GND
VDIFF VSEN RGND VTT VR_RDY VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI VR_FAN VR_HOT VIN VCC EN_PWR PWM PWM4 IMON TCOMP TM +5V +5V UGATE VCC NTC ISL6612 DRIVER LGATE PWM GND PHASE OFS FS ISEN4ISL6612 DRIVER LGATE GND PWM3 ISEN3ISEN3+ UGATE PHASE +12V +5V BOOT PVCC P LOAD PWM2 ISEN2ISEN2+ PWM UGATE EN_VTT PWM1 ISEN1ISEN1+
+5V +12V
BOOT PVCC
VIN
ISL6334 ISL6334
VCC
PHASE ISL6612 DRIVER LGATE GND
VIN
GND
ISEN4+
+5V SS +12V BOOT PVCC VIN
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FN6601.2 March 19, 2009
ISL6622A
Absolute Maximum Ratings
Supply Voltage (VCC, UVCC, LVCC) . . . . . . . . . . . . . . . . . . . . .15V BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V VPHASE - 3.5V (<100ns Pulse Width, 2J) to VBOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3VDC to VLVCC + 0.3V GND - 5V (<100ns Pulse Width, 2J) to VLVCC + 0.3V PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC GND - 8V (<400ns, 20J) to 30V (<200ns, VBOOT-GND < 36V)
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) SOIC Package (Note 1) . . . . . . . . . . . . 100 N/A DFN Package (Notes 2, 3) . . . . . . . . . . 48 7 Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range ISL6622AIBZ, ISL6622AIRZ . . . . . . . . . . . . . . . . .-40C to +85C ISL6622ACBZ, ISL6622ACRZ . . . . . . . . . . . . . . . . . 0C to +70C Maximum Operating Junction Temperature. . . . . . . . . . . . . +125C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V Supply Voltage Range, UVCC . . . . . . . . . . . . . . . . . 4.75V to 13.2V Supply Voltage Range, LVCC . . . . . . . . . . . . . . . . . . 4.75V to 13.2V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 4. Limits should be considered typical and are not production tested.
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER VCC SUPPLY CURRENT (Note 4) No Load Switching Supply Current
IVCC ILVCC IVCC ILVCC IUVCC
ISL6622ACBZ and ISL6622AIBZ, fPWM = 300kHz, VVCC = 12V ISL6622ACRZ and ISL6622AIRZ, fPWM = 300kHz, VVCC = 12V
-
7 3.5 4 3.5 3 5.5 0.15 5 0.15 0.5
-
mA mA mA mA mA mA mA mA mA mA
Standby Supply Current
IVCC ILVCC IVCC ILVCC IUVCC
ISL6622ACBZ and ISL6622AIBZ, PWM Transition from 0V to 2.5V ISL6622ACRZ and ISL6622AIRZ, PWM Transition from 0V to 2.5V
-
POWER-ON RESET VCC Rising Threshold VCC Falling Threshold LVCC Rising Threshold LVCC Falling Threshold PWM INPUT (See "TIMING DIAGRAM" on page 6) Input Current (Note 4) IPWM VPWM = 5V VPWM = 0V PWM Rising Threshold (Note 4) PWM Falling Threshold (Note 4) Three-State Lower Gate Falling Threshold (Note 4) Three-State Lower Gate Rising Threshold (Note 4) VCC = 12V VCC = 12V VCC = 12V VCC = 12V 500 -430 3.4 1.6 1.6 1.1 A A V V V V 6.25 4.8 4.25 3.3 6.45 5.0 4.4 3.4 6.70 5.25 4.55 3.55 V V V V
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ISL6622A
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL TEST CONDITIONS VCC = 12V VCC = 12V tRU tRL tFU tFL tPDHU tPDHL tPDLU tPDLL tPDTS tLG_ON_DM IU_SOURCE IU_SINK RU_SINK IL_SOURCE IL_SINK RL_SINK VVCC = 12V, 3nF Load, 10% to 90% VVCC = 12V, 3nF Load, 10% to 90% VVCC = 12V, 3nF Load, 90% to 10% VVCC = 12V, 3nF Load, 90% to 10% VVCC = 12V, 3nF Load, Adaptive VVCC = 12V, 3nF Load, Adaptive VVCC = 12V, 3nF Load VVCC = 12V, 3nF Load VVCC = 12V, 3nF Load VVCC = 12V VVCC = 12V, 3nF Load VVCC = 12V, 3nF Load 20mA Sink Current VVCC = 12V, 3nF Load VVCC = 12V, 3nF Load 20mA Sink Current MIN 230 TYP 3.2 2.8 26 18 18 12 20 10 10 10 10 60 330 MAX 450 UNITS V V ns ns ns ns ns ns ns ns ns ns ns
PARAMETER Three-State Upper Gate Rising Threshold (Note 4) Three-State Upper Gate Falling Threshold (Note 4) UGATE Rise Time (Note 4) LGATE Rise Time (Note 4) UGATE Fall Time (Note 4) LGATE Fall Time (Note 4) UGATE Turn-On Propagation Delay (Note 4) LGATE Turn-On Propagation Delay (Note 4) UGATE Turn-Off Propagation Delay (Note 4) LGATE Turn-Off Propagation Delay (Note 4) LG/UG Three-State Propagation Delay (Note 4) Diode Braking Holdoff Time (Note 4) Minimum LGATE On-Time at Diode Emulation OUTPUT (Note 4) Upper Drive Source Current Upper Drive Source Impedance Upper Drive Sink Current Upper Drive Sink Impedance Lower Drive Source Current Lower Drive Source Impedance Lower Drive Sink Current Lower Drive Sink Impedance
tUG_OFF_DB VVCC = 12V
-
1.25 2 2 1.35 2 1.35 3 0.9
-
A A A A
RU_SOURCE 20mA Source Current
RL_SOURCE 20mA Source Current
Functional Pin Descriptions
PACKAGE PIN # SOIC 1 2 DFN 1 2 PIN SYMBOL UGATE BOOT FUNCTION Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET. Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See "Internal Bootstrap Device" on page 7 for guidance in choosing the capacitor value. No Connect The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation; see "Description" on page 6 for further details. Connect this pin to the PWM output of the controller. Bias and reference ground. All signals are referenced to this node. It is also the power-ground return of the driver. Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET. This pin supplies power to the lower gate drive. Its operating range is +5V to +12V. Place a high quality low ESR ceramic capacitor from this pin to GND. This pin supplies power to the upper gate drive. Its operating range is +5V to +12V. Place a high quality low ESR ceramic capacitor from this pin to GND. Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC. Place a high quality low ESR ceramic capacitor from this pin to GND. Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a return path for the upper gate drive. Connect this pad to the power ground plane (GND) via thermally enhanced connection.
3 4 5 6 7 8 -
3 4 5 6 7 8 9 10 11
NC PWM GND LGATE LVCC UVCC VCC PHASE PAD
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FN6601.2 March 19, 2009
ISL6622A
1.5V < PWM < 3.2V PWM 1.0V< PWM < 2.6V
tPDHU
tPDLU tPDTS tFU tUG_OFF_DB tPDTS
UGATE
tRU
LGATE tFL tPDLL tPDHL tRL tTSSHD
FIGURE 1. TIMING DIAGRAM
Description
Operation and Adaptive Shoot-through Protection
Designed for high speed switching, the ISL6622A MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal. A rising transition on PWM initiates the turn-off of the lower MOSFET (see Figure 1). After a short propagation delay [tPDLL], the lower gate begins to fall. Typical fall time [tFL] is provided in the "Electrical Specifications" on page 5. Following a 25ns blanking period, adaptive shoot-through circuitry monitors the LGATE voltage and turns on the upper gate following a short delay time [tPDHU] after the LGATE voltage drops below ~1.75V. The upper gate drive then begins to rise [tRU] and the upper MOSFET turns on. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLU] is encountered before the upper gate begins to fall [tFU]. The adaptive shoot-through circuitry monitors the UGATE-PHASE voltage and turns on the lower MOSFET a short delay time [tPDHL] after the upper MOSFET's PHASE voltage drops below +0.8V or 40ns after the upper MOSFET's gate voltage [UGATE-PHASE] drops below ~1.75V. The lower gate then rises [tRL], turning on the lower MOSFET. These methods prevent both the lower and upper MOSFETs from conducting simultaneously (shoot-through), while adapting the dead-time to the gate charge characteristics of the MOSFETs being used. This driver is optimized for voltage regulators with large step down ratio. The lower MOSFET is usually sized larger compared to the upper MOSFET because the lower MOSFET conducts for a longer time during a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.8 ON-resistance and 3A sink current capability enable the lower gate driver to absorb the current injected into the lower gate through the drain-to-gate capacitor of the lower MOSFET and help prevent
shoot-through caused by the self turn-on of the lower MOSFET due to high dV/dt of the switching node.
Advanced PWM Protocol (Patent Pending)
The advanced PWM protocol of ISL6622A is specifically designed to work with Intersil VR11.1 controllers. When ISL6622A detects a PSI protocol sent by an Intersil VR11.1 controller, it turns on diode emulation operation; otherwise, it remains in normal CCM PWM mode. Another unique feature of ISL6622A and other Intersil drivers is the addition of a three-state shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the driver outputs are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the "Electrical Specifications" on page 4 determine when the lower and upper gates are enabled. This feature helps prevent a negative transient on the output voltage when the output is shut down, eliminating the Schottky diode that is used in some systems for protecting the load from reversed output voltage events. Note that the LGATE will not turn off until the diode emulation minimum LGATE ON-time of 350ns is expired for a PWM low to tri-level (2.5V) transition.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored. Once the rising VCC voltage exceeds rising POR threshold, operation of the driver is enabled and the PWM input signal takes control of the gate drives. If VCC drops below the falling threshold, operation of the driver is disabled.
Pre-POR Overvoltage Protection
While VCC is below its POR level, the upper gate is held low and LGATE is connected to the PHASE pin via an internal 10k (typically) resistor. By connecting the PHASE node to the gate of the low side MOSFET, the driver offers some passive
FN6601.2 March 19, 2009
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ISL6622A
protection to the load if the upper MOSFET(s) is or becomes shorted. If the PHASE node goes higher than the gate threshold of the lower MOSFET, it results in the progressive turn-on of the device and the effective clamping of the PHASE node's rise. The actual PHASE node clamping level depends on the lower MOSFET's electrical characteristics, as well as the characteristics of the input supply and the path connecting it to the respective PHASE node. upper gate drive is fixed to VCC [+12V] in the SOIC, but the lower drive rail can be driven from 5V to 12V using the LVCC pin. In the DFN package, a separate UVCC pin is available for the upper gate drive voltage to be driven from 5V to 12V for efficiency optimization, while the lower gate can be driven independently using the LVCC pin from 5V to 12V.
Diode Emulation
Diode emulation allows for higher converter efficiency under light-load situations. With diode emulation active, the ISL6622A detects the zero current crossing of the output inductor and turns off LGATE. This prevents the low side MOSFET from sinking current and ensures that discontinuous conduction mode (DCM) is achieved. The LGATE has a minimum on-time of 350ns in DCM mode.
Internal Bootstrap Device
The ISL6622A features an internal bootstrap Schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the trailing-edge of the PHASE node. This reduces voltage stress on the BOOT to PHASE pins.
1.6 1.4 1.2 CBOOT_CAP (F) 1.0 0.8 0.6 QGATE = 100nC 0.4 50nC 0.2 20nC 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Power Dissipation
Package power dissipation is mainly a function of the switching frequency (FSW), the output drive impedance, the external gate resistance, and the selected MOSFET's internal gate resistance and total gate charge. Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level may push the IC beyond the maximum recommended operating junction temperature. The DFN package is more suitable for high frequency applications. See "Layout Considerations" on page 8 for thermal transfer improvement suggestions. When designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses due to the gate charge of MOSFETs and the driver's internal circuitry and their corresponding average driver current can be estimated with Equations 2 and 3, respectively:
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q * VCC Q G1 * UVCC 2 P Qg_Q1 = -------------------------------------- * F SW * N Q1 V GS1 Q G2 * LVCC 2 P Qg_Q2 = ------------------------------------- * F SW * N Q2 V GS2 Q G1 * UVCC * NQ1 Q G2 * LVCC * N Q2 I DR = ----------------------------------------------------- + ---------------------------------------------------- * F SW + I Q V GS1 V GS2 (EQ. 3) (EQ. 2)
0.0 0.0
VBOOT_CAP (V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
The bootstrap capacitor must have a maximum voltage rating well above the maximum voltage intended for UVCC. Its minimum capacitance value can be chosen from Equation 1.
Q GATE C BOOT_CAP ------------------------------------V BOOT_CAP Q G1 * UVCC Q GATE = ----------------------------------- * N Q1 V GS1
(EQ. 1)
where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. Select results are exemplified in Figure 2.
Gate Drive Voltage Versatility
The ISL6622A provides the user flexibility in choosing the gate drive voltage for efficiency optimization. The ISL6622A
where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET data sheet; IQ is the driver's total quiescent current with no load at both drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively; UVCC and LVCC are the drive voltages for both upper and lower FETs, respectively. The IQ*VCC product is the quiescent power of the driver without capacitive load.
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ISL6622A
The total gate drive power losses are dissipated among the resistive components along the transition path, as outlined in Equation 4. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (RG1 and RG2) and the internal gate resistors (RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the typical upper and lower gate drives turn-on current path.
P DR = P DR_UP + P DR_LOW + I Q * VCC R LO1 R HI1 P Qg_Q1 P DR_UP = -------------------------------------- + --------------------------------------- * --------------------R HI1 + R EXT1 R LO1 + R EXT1 2 R LO2 R HI2 P Qg_Q2 P DR_LOW = -------------------------------------- + --------------------------------------- * --------------------2 R HI2 + R EXT2 R LO2 + R EXT2 R GI1 R EXT1 = R G1 + ------------N
Q1
* Minimize trace inductance, especially low-impedance lines: all power traces (UGATE, PHASE, LGATE, GND, LVCC) should be short and wide, as much as possible. * Minimize the inductance of the PHASE node: ideally, the source of the upper and the drain of the lower MOSFET should be as close as thermally allowable. * Minimize the input current loop: connect the source of the lower MOSFET to ground as close to the transistor pin as feasible; input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower MOSFETs as possible. In addition, for improved heat dissipation, place copper underneath the IC whether it has an exposed pad or not. The copper area can be extended beyond the bottom area of the IC and/or connected to buried power ground plane(s) with thermal vias. This combination of vias for vertical heat escape, extended surface copper islands, and buried planes combine to allow the IC and the power switches to achieve their full thermal potential.
(EQ. 4)
R GI2 R EXT2 = R G2 + ------------N
Q2
UVCC
BOOT D CGD RHI1 RLO1 G RG1 RGI1 CGS S PHASE Q1 CDS
Upper MOSFET Self Turn-On Effects At Startup
Should the driver have insufficient bias voltage applied, its outputs are floating. If the input bus is energized at a high dV/dt rate while the driver outputs are floating, due to self-coupling via the internal CGD of the MOSFET, the gate of the upper MOSFET could momentarily rise up to a level greater than the threshold voltage of the device, potentially turning on the upper switch. Therefore, if such a situation could conceivably be encountered, it is a common practice to place a resistor (RUGPH) across the gate and source of the upper MOSFET to suppress the Miller coupling effect. The value of the resistor depends mainly on the input voltage's rate of rise, the CGD/CGS ratio, as well as the gate-source threshold of the upper MOSFET. A higher dV/dt, a lower CDS/CGS ratio, and a lower gate-source threshold upper FET will require a smaller resistor to diminish the effect of the internal capacitive coupling. For most applications, the integrated 20k resistor is sufficient, not affecting normal performance and efficiency. The coupling effect can be roughly estimated with Equation 5, which assumes a fixed linear input ramp and neglects the clamping effect of the body diode of the upper drive and the bootstrap capacitor. Other parasitic components such as lead inductances and PCB capacitances, are also not taken into account. Figure 5 provides a visual reference for this phenomenon and its potential solution.
DS --------------------------------- dV ------ R C dV iss 1 - e dt V GS_MILLER = ------ R C rss dt -V
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
LVCC D CGD RHI2 RLO2 G RG2 RGI2 CGS S Q2 CDS
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
Layout Considerations
During switching of the devices, the parasitic inductances of the PCB and the power devices' packaging (both upper and lower MOSFETs) leads to ringing, possibly in excess of the absolute maximum rating of the devices. Careful layout can help minimize such unwanted stress. The following advice is meant to lead to an optimized layout: * Keep decoupling loops (LVCC-GND and BOOT-PHASE) as short as possible.
(EQ. 5)
R = R UGPH + R GI
C rss = C GD
C iss = C GD + C GS
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ISL6622A
Gate Drive Voltage Options
UVCC BOOT CBOOT UGATE ISL6622A DU RUGPH DL G RGI CGS S PHASE QUPPER CGD CDS VIN D
Intersil provides various gate drive voltage options in ISL6622 product family, as shown in Table 2. The ISL6622 can drop the low-side MOSFET's gate drive voltage when operating in DEM, while the high-side FET's gate drive voltage of the DFN package can be connected to VCC or LVCC. The ISL6622A allows the low-side MOSFET(s) to operate from an externally-provided rail as low as 5V, eliminating the LDO losses, while the high-side MOSFET's gate drive voltage of the DFN package can be connected to VCC or LVCC. The ISL6622B sets the low-side MOSFET's gate drive voltage at a fixed, programmable LDO level, while the highside FETs' gate drive voltage of the DFN package can be connected to VCC or LVCC.
FIGURE 5. GATE-TO-SOURCE RESISTOR TO REDUCE UPPER MOSFET MILLER COUPLING
TABLE 1. ISL6622 FAMILY OPTIONS LVCC POWER RAILS ISL6622 SOIC DFN ISL6622A SOIC DFN ISL6622B SOIC DFN PSI = LOW 5.75V Programmable Own Rail Own Rail 5.75V Programmable PSI = HIGH 11.2V 11.2V UVCC VCC Own Rail VCC Own Rail VCC Own Rail VCC Operating Voltage Ranges from 6.8V to 13.2V
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FN6601.2 March 19, 2009
ISL6622A Dual Flat No-Lead Plastic Package (DFN)
2X 0.15 C A A D 2X 0.15 C B
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 MIN 0.80 0.18 1.95 1.55 0.25 0.30 NOMINAL 0.90 0.20 REF 0.23 3.00 BSC 2.00 3.00 BSC 1.60 0.50 BSC 0.35 10 5 0.40 1.65 2.05 0.28 MAX 1.00 0.05 NOTES 5,8 7,8 7,8 8 2 3 Rev. 3 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
E 6 INDEX AREA TOP VIEW B
A3 b D D2 E E2
0.10 C
e k L N Nd
A 0.08 C C SEATING PLANE SIDE VIEW A3
7 (DATUM B) 6 INDEX AREA (DATUM A) 1 2 D2
8
D2/2 NX k E2 E2/2
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW 5 0.10 M C A B
C L 0.415 NX (b) 5 SECTION "C-C" C NX b (A1) 0.200 L NX L e CC TERMINAL TIP
FOR ODD TERMINAL/SIDE
10
FN6601.2 March 19, 2009
ISL6622A Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6601.2 March 19, 2009

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